Failure Analysis (FA) is a process performed to discern the causes of failures of semiconductor dies. Failure analysis can be performed while a die is still in the design phase or even after commercial quantities of a die have been produced and marketed.
One conventional failure analysis technique involves deprocessing a die, layer by layer, and visually inspecting the inside of the die, usually by microscope or other imaging device, to discover the cause of failure. When using high-magnification microscopy (e.g., during micro-probing), the field of view seen by a human operator is very small compared to the overall area of the die, and it is often time consuming for a human operator to determine which portion of the die is in the field of view.
One conventional solution is shown in FIG. 1. FIG. 1 is a top-down schematic illustration of a die layout 100. The die layout 100 includes a number of logic cells, such as a logic cell 101, which may include AND gates, NAND gates, OR gates and/or the like. The die layout 100 also includes fiducial markers, such as a fiducial marker 102, which indicates a position to a human user or computer. In other words, during failure analysis, a human user employing microscopy can use the fiducial markers as an indication of location within the die as well as for navigation from place to place within the die. Of note in die layout 100 is the regular pattern in which the fiducial markers are laid out. Such conventional approach places the fiducial markers before placing the cells. A disadvantage of such approach is that the placement of fiducial markers affects the placement of the cells, resulting in a less than optimal cell placement.